戴尔 R730 风扇转速过高 噪声过大 调整记录

昨天安装新服务器的时候发现了一个问题,那就是当服务器进入操作系统之后风扇转速便超过了80%,在BIOS里边设置风扇的策略也没有任何效果,最后找到了原因,仅记录之。服务器使用的型号是Dell R730刀片机服务器。

经过昨天一下午的奋斗,发现服务器风扇转速过高的问题出在服务器对显卡温度的监测上,由于显卡使用的是AMD 的 wx9100,是主动散热卡,而服务器会不停的尝试加大风扇转速来控制显卡的温度,导致温度过高。(容我吐槽mdzz)

所以解决方法是首先在iDRC里边打开IPMI远程登录功能,然后再使用ipmitools关闭其对PCIe温度的检测。

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ipmitool -I lanplus -H hostip -U username -P password raw 0x30 0xce 0x00 0x16 0x05 0x00 0x00 0x00 0x05 0x00 0x01 0x00 0x00

如果正常运行服务器会返回:

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0x16 0x05 0x00 0x00

然后服务器风扇回归正常。

(完)

AMD Radeon Vega Frontier Edition 与 Windows Server 2016 的调整小记

最近入手了一块农企的显卡,Vega Frontier Edition。本来是一件令人兴奋的事情,但是在使用的过程中碰到了很多这样或者那样的问题,仅把一些问题以及其解决方案记录下来。

首先说明一下我的平台配置:
Windows 版本 – Windows Server 2016 Datacenter
系统内存 – 32 GB
CPU 类型 – Intel(R) Xeon(R) CPU E5-2678 v3 @ 2.50GHz

前两天在AMD官网上寻找驱动的时候,有两个版本的驱动,一个是17.12.2 版本的Adrenalin Edition,另一个是18.Q1版本的Enterprise Edition 但是经过测试,仅有17.12.2版本的驱动可以安装在我的平台上,(后来用其他平台测试证实,是由于操作系统的版本导致的在新版Win10上可以正常运行,初步怀疑是和系统内核版本有关系)邮件咨询AMD后回复是:

由于Vega Frontier Edition显卡不是服务器显卡,暂时没有提供Windows Server下的驱动,故当您安装驱动时显示无法正确安装。建议您使用提供驱动的Win7/10 64位系统。

所以以下测试均基于17.12.2版本驱动。(但事实上很多问题的解决方法并不局限于此版本)

首先第一个问题就出在其显卡驱动模式切换上。根据宣传,这张卡有专用的驱动可以支持游戏模式和专业模式的切换,以满足开发和游戏有共同需求的群体(还有有信仰的人群体)。但是在切换显卡的时候会出现驱动程序回滚的情况。比方说在从17.12.2专业版切换到17.12.2游戏版的时候,往往会在切换完成后自动回滚至17.7游戏版,导致很多新游戏无法体验。这个问题的原因尚不明确,主要还是系统兼容性问题,由于AMD显卡驱动会在出现问题的时候自动回滚,所以在切换显卡驱动模式的时候,总有很大概率出发一些未知的错误。

这里的解决方法是打开设备管理器,找到显卡的驱动,点击更新驱动,在浏览计算机上的驱动程序里边点从驱动程序列表中选取,双击重新安装即可解决。

第二个问题出在其显卡温度控制策略上。在游戏模式下,其温度策略和电源控制可以用WattMan来调整,非常方便。但是在专业模式下,其并没有提供这样的一个工具。但是其默认的温度控制策略并不尽人意,风扇转速最高2000转,然而即便达到2000转,也很难维持核心温度不高于95度,尤其是在使用ProRender进行渲染的时候,常常会因为过热保护而导致程序出错,十分闹心。

后来想来想去想通过修改显卡vBIOS的手段来改变其温度控制策略,进行了一些尝试,由于没有现成的Vega BIOS Editor这样的修改工具,所以选择使用UE进行编辑,屡次尝试刷入BIOS均失败。后来发现在Vega之后,显卡的BIOS都进行了签名或者之类的操作,导致用户无法自行编辑BIOS。(好在显卡有双BIOS,可以在尝试失败后恢复原来的BIOS)

后来在网上找到了一个解决方法,即修改注册表的方法,其原理是通过给注册表中添加PowerPlay表,来调整显卡的策略。虽然具体的原理不是很了解,但是根据我的推测,由于这个PowerPlay表可以在vBIOS中可以找到一模一样的一段数据,应该就是显卡的电源温度频率等一些参数的配置表格,vBIOS中有一默认的,而驱动修改后的则会储存在注册表中方便调用。

由于其在注册表中的结构和其在vBIOS中的结构一致,所以在解析其结构的时候可以参照Linux中对于AMD显卡的参数处理:GitHub-torvalds/linux

以下为我根据我的需求修改了之后的注册表文件以及原版注册表文件。设置了最高风扇转速为4000转,最低转速为1000转,并在显卡温度低于40摄氏度时关闭散热风扇,在温度高于45度时重新开启。转速自动调整并控制显卡温度不超过70摄氏度。

MorePowerVegaFE-default

MorePowerVegaFE-optimized

我修改的过程则参考国外的一篇帖子:Preliminary view of AMD VEGA Bios

这篇帖子以Vega 64/Vega 56为例,列举了一些参数的修改和超频方法,其主要目的在于Vega 64/Vega 56的超频测试,由于我只需要修改其中的温度控制部分,所以我参照了这个结构体:

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typedef struct _ATOM_Vega10_Fan_Table_V2 {
0B UCHAR ucRevId;
E4 12 (0x12E4 = 4836)     USHORT usFanOutputSensitivity;
AC 0D (0xDAC = 3500 RPM)  USHORT usFanAcousticLimitRpm;
AC 0D (0xDAC = 3500 RPM)  USHORT usThrottlingRPM;
46 00 (0x46 = 70°C)       USHORT usTargetTemperature;
23 00 (0x23 = 35)         USHORT usMinimumPWMLimit;
54 03 (0x354 = 852)       USHORT usTargetGfxClk;
90 01 (0x190 = 400)       USHORT usFanGainEdge;
90 01 (0x190 = 400)       USHORT usFanGainHotspot;
90 01 (0x190 = 400)       USHORT usFanGainLiquid;
90 01 (0x190 = 400)       USHORT usFanGainVrVddc;
90 01 (0x190 = 400)       USHORT usFanGainVrMvdd;
90 01 (0x190 = 400)       USHORT usFanGainPlx;
90 01 (0x190 = 400)       USHORT usFanGainHbm;
01 (01 = on / 00 = off)   UCHAR ucEnableZeroRPM;
28 00 (0x28 = 40°C)       USHORT usFanStopTemperature;
32 00 (0x32 = 50°C)       USHORT usFanStartTemperature;
02                        UCHAR ucFanParameters;
08 (800 RPM)              UCHAR ucFanMinRPM;
23 (0x23 = 35 = 3500 RPM) UCHAR ucFanMaxRPM;
} ATOM_Vega10_Fan_Table_V2;

而如果想要修改其频率和电源策略的话,如果仅是修改最高状态,进行跑分测试,则完全可以参考原贴中的修改方式,而如果想要自己设置频率曲线或者显存频率曲线,则需要自行参考代码进行。

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typedef struct _ATOM_Vega10_POWERPLAYTABLE {
    typedef struct _ATOM_COMMON_TABLE_HEADER
    {
    B6 02 (0x2B6)  USHORT usStructureSize;
    08             UCHAR  ucTableFormatRevision;   /*Change it when the Parser is not backward compatible */
    01             UCHAR  ucTableContentRevision;  /*Change it only when the table needs to change but the firmware */
                                                   /*Image can't be updated, while Driver needs to carry the new table! */
    } ATOM_COMMON_TABLE_HEADER;
00                      UCHAR  ucTableRevision;
5C 00                   USHORT usTableSize;                        /* the size of header structure */
E1 06 00 00             ULONG  ulGoldenPPID;                       /* PPGen use only */
EE 2B 00 00             ULONG  ulGoldenRevision;                   /* PPGen use only */
1B 00                   USHORT usFormatID;                         /* PPGen use only */
48 00 00 00             ULONG  ulPlatformCaps;                     /* See ATOM_Vega10_CAPS_* */
80 A9 03 00 (2400MHz)   ULONG  ulMaxODEngineClock;                 /* For Overdrive. */
F0 49 02 00 (1500MHz)   ULONG  ulMaxODMemoryClock;                 /* For Overdrive. */
32 00                   USHORT usPowerControlLimit;
08 00                   USHORT usUlvVoltageOffset;                 /* in mv units */
00 00                   USHORT usUlvSmnclkDid;
00 00                   USHORT usUlvMp1clkDid;
00 00                   USHORT usUlvGfxclkBypass;
00 00                   USHORT usGfxclkSlewRate;
00                      UCHAR  ucGfxVoltageMode;
00                      UCHAR  ucSocVoltageMode;
00                      UCHAR  ucUclkVoltageMode;
00                      UCHAR  ucUvdVoltageMode;
00                      UCHAR  ucVceVoltageMode;
02                      UCHAR  ucMp0VoltageMode;
01                      UCHAR  ucDcefVoltageMode;
5C 00 (0x5C)            USHORT usStateArrayOffset;                 /* points to ATOM_Vega10_State_Array */
4F 02 (0x24F)           USHORT usFanTableOffset;                   /* points to ATOM_Vega10_Fan_Table */
46 02 (0x246)           USHORT usThermalControllerOffset;          /* points to ATOM_Vega10_Thermal_Controller */
94 00 (0x94)            USHORT usSocclkDependencyTableOffset;      /* points to ATOM_Vega10_SOCCLK_Dependency_Table */
9E 01 (0x19E)           USHORT usMclkDependencyTableOffset;        /* points to ATOM_Vega10_MCLK_Dependency_Table */
BE 00 (0xBE)            USHORT usGfxclkDependencyTableOffset;      /* points to ATOM_Vega10_GFXCLK_Dependency_Table */
28 01 (0x128)           USHORT usDcefclkDependencyTableOffset;     /* points to ATOM_Vega10_DCEFCLK_Dependency_Table */
7A 00 (0x7A)            USHORT usVddcLookupTableOffset;            /* points to ATOM_Vega10_Voltage_Lookup_Table */
8C 00 (0x8C)            USHORT usVddmemLookupTableOffset;          /* points to ATOM_Vega10_Voltage_Lookup_Table */
BC 01 (0x1BC)           USHORT usMMDependencyTableOffset;          /* points to ATOM_Vega10_MM_Dependency_Table */
00 00                   USHORT usVCEStateTableOffset;              /* points to ATOM_Vega10_VCE_State_Table */
00 00                   USHORT usReserve;                          /* No PPM Support for Vega10 */
72 02 (0x272)           USHORT usPowerTuneTableOffset;             /* points to ATOM_Vega10_PowerTune_Table */
00 00                   USHORT usHardLimitTableOffset;             /* points to ATOM_Vega10_Hard_Limit_Table */
90 00 (0x90)            USHORT usVddciLookupTableOffset;           /* points to ATOM_Vega10_Voltage_Lookup_Table */
A8 02 (0x2A8)           USHORT usPCIETableOffset;                  /* points to ATOM_Vega10_PCIE_Table */
6D 01 (0x16D)           USHORT usPixclkDependencyTableOffset;      /* points to ATOM_Vega10_PIXCLK_Dependency_Table */
43 01 (0x143)           USHORT usDispClkDependencyTableOffset;     /* points to ATOM_Vega10_DISPCLK_Dependency_Table */
97 01 (0x197)           USHORT usPhyClkDependencyTableOffset;      /* points to ATOM_Vega10_PHYCLK_Dependency_Table */
} ATOM_Vega10_POWERPLAYTABLE;

上面这个表格是PowerPlay的Header结构体,里面包含了很多其它表格的地址等,值得注意的是,如果将我提供的注册表中的文件中16进制的第一字节定义为0地址,则该表格中所有的Table的地址指针需要减去0x34.

所有表格的结构均可参考Linux驱动中的vega10_pptable.h文件将数据与结构体一一比对即可。

(完)

ADF4251 锁相环 使用笔记 (配合HAL库)

之前在比赛准备的时候有准备过关于锁相环相关的器件,这里介绍一下ADF4351这款宽带频率合成器的使用。

由于我使用的是购买来的成品模块,所以这里着重讲的是软件驱动方面。

ADF4351 用户手册

首先根据手册可以看到,这是一款35MHz到4.4GHz的锁相环芯片,具有低相位噪声等优点,同时支持小数和整数分频。其实它的VCO是2.2GHz到4.4GHz的振荡器,其余35MHz到2.2GHz全部是由可编程的输出分频器分频得到的。这款芯片的性能是非常好的,输出的信号相位噪声很低,手册上给出的数据是−100dBc/Hz 3 kHz from 2111.28 MHz carrier,在实际测试中发现我手中的这块芯片甚至略微超出了这个参数。

接下来关注到,其配置方式是通过一个3-wire的串行总线完成的,那么可以关注一下这个总线的通信时序:

从时序可以看出,这个三线串口中,有一条使能线,一条时钟线和一条数据线,这个三线串口其实就是SPI接口,所以我们可以直接调用单片机的硬件SPI模块来与其通信。并且需要注意的是,在这个协议当中,后三位表示的是寄存器的编号,而且这个协议的速率不应该高于20Mbps。

关于如何配置这块芯片,就需要大致的了解一下它的工作原理。首先向其输入一个REF-in的参考输入信号,然后这个参考信号在通过一个缓冲器之后,会进入一个名为R counter的计数器中,这里呢就使用了计数器对输入的参考信号进行分频,这一步的分频可以使得分频后的信号拥有更小的相位噪声。同时,由压控振荡器VCO产生的信号经过N counter计数器后,一并通入鉴频鉴相器中。最后将鉴频鉴相器的输入通入电荷泵,通过电荷泵后的电压再用来控制VCO。所以输出频率的计算公式即为:

但是需要注意的是,RF_OUT的值必须是一个2.2G到4.4G之间的值,因为它是压控振荡器VCO的输出值。而最终芯片的输出频率35MHz-4.4GHz需要将RF_OUT的输出值再进行一个2的次方倍分频才行。

关于寄存器的功能,便不再详述,手册上写的非常详尽。

最后附上代码(双击代码区域复制):

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/**
  ******************************************************************************
  * File Name          : main.c
  * Description        : Main program body
  ******************************************************************************
  *
  * COPYRIGHT(c) 2017 STMicroelectronics
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32f1xx_hal.h"
 
/* USER CODE BEGIN Includes */
 
/* USER CODE END Includes */
 
/* Private variables ---------------------------------------------------------*/
CRC_HandleTypeDef hcrc;
 
IWDG_HandleTypeDef hiwdg;
 
SPI_HandleTypeDef hspi2;
 
TIM_HandleTypeDef htim6;
TIM_HandleTypeDef htim7;
 
WWDG_HandleTypeDef hwwdg;
 
/* USER CODE BEGIN PV */
/* Private variables ---------------------------------------------------------*/
#define PLL_PROT hspi2
typedef struct PLL_Configure{
	enum{
		PLL_DISABLE = 0,
		PLL_ENABLE
	};
	unsigned short integer_value;						//16-bit Greater than 23, to 65535
	unsigned short fractional_value;				//12-bit 0 to 4095
	unsigned char phase_adjust;							//1-bit 0-OFF 1-ON
	enum{
		PHASE_ADJ_OFF = 0,
		PHASE_ADJ_ON
	}phase_adjust_type;
	//unsigned char prescaler;								//1-bit 0-(4/5) 1-(8/9)
	enum prescaler_type{
		PRESCALER_4Div5 = 0,
		PRESCALER_8Div9
	}prescaler;
	//enum prescaler_type prescaler;
	unsigned short phase_value;							//12-bit 0 to 4095, 1 is recommended
	unsigned short modulus_value;						//12-bit Greater than 2, to 4095
	unsigned char low_noise_and_low_spur;		//2-bit 00b-(Low Noise Mode) 11b-(Low Spur Mode)
	enum{
		LOW_NOISE = 0,
		LOW_SUPR = 3
	}low_nose_and_low_spur_type;
	unsigned char muxout;										//3-bit
	enum{
		MUXOUT_Three_State_Output = 0,
		MUXOUT_DVdd,
		MUXOUT_DGND,
		MUXOUT_R_COUNTER,
		MUXOUT_N_DIVIDER,
		MUXOUT_ANALOG_LOCK_DETECT,
		MUXOUT_DIGITAL_LOCK_DETECT,
		MUXOUT_RESERVED
	}muxout_type;
	//000b-Three-State Output
	//001b-DVdd
	//010b-DGND
	//011b-R Counter Output
	//100b-N Divider Output
	//101b-Analog Lock Detect
	//110b-Digital Lock Detect
	//111b-Reserved
	unsigned char reference_doubler;				//1-bit 0-Disable 1-Enable
	unsigned char reference_divide_by2;			//1-bit 0-Disable 1-Enable
	unsigned short r_counter;								//10-bit Greater than 1, to 1023
	unsigned char double_buffer;						//1-bit 0-Disable 1-Enable
	unsigned char charge_pump_current;			//4-bit 0 to 15
	/*CHARGE PUMP CURRENT SETTING VALUE
	0000 0.31
	0001 0.63
	0010 0.94
	0011 1.25
	0100 1.56
	0101 1.88
	0110 2.19
	0111 2.50
	1000 2.81
	1001 3.13
	1010 3.44
	1011 3.75
	1100 4.06
	1101 4.38
	1110 4.69
	1111 5.00*/
	unsigned char LDF;											//1-bit 0-FRAC-N 1-INT-N
	enum{
		FRAC_N = 0,
		INT_N
	}LDF_type;
	unsigned char LDP;											//1-bit 0-10ns 1-6ns
	enum{
		LDP_10ns = 0,
		LDP_6ns
	}LDP_type;
	unsigned char PD_polarity;							//1-bit 0-NEGTIVE 1-POSITIVE
	enum{
		NEGTIVE = 0,
		POSITIVE
	}PD_polarity_type;
	unsigned char power_down;								//1-bit 0-Disable 1-Enable
	unsigned char CP_three_state;						//1-bit 0-Disable 1-Enable
	unsigned char counter_reset;						//1-bit 0-Disable 1-Enable
	unsigned char band_select_clock;				//1-bit 0-LOW 1-HIGH
	enum{
		LOW = 0,
		HIGH
	}band_select_clock_type;
	unsigned char antibacklash_pulse_width;	//1-bit 0-6ns 1-3ns
	enum{
		ANTIBACKLASH_PULSE_6ns = 0,
		ANTIBACKLASH_PULSE_3ns
	}antibacklash_pulse_type;
	unsigned char charge_cancelation;				//1-bit 0-Disable 1-Enable
	unsigned char cycle_slip_reduction;			//1-bit 0-Disable	1-Enable
	unsigned char clk_div_mode;							//2-bit
	enum{
		CLOCK_DIVIDER_OFF = 0,
		FAST_LOCK_ENABLE,
		RESYNC_ENABLE
	}clk_div_mode_type;
	unsigned short clock_divider_value;			//12-bit 0 to 4095
	unsigned char feedback_select;					//1-bit 0-Divided 1-Fundamental
	enum{
		DIVIDED = 0,
		FUNDAMENTAL
	}feedback_select_type;
	unsigned char RF_divider_select;				//3-bit
	/*RF DIVIDER SELECT
	000 /1
	001 /2
	010 /4
	011 /8
	100 /16
	101 /32
	110 /64
	*/
	unsigned char band_select_clock_divider;//8-bit Greater than 1, to 255
	unsigned char VCO_power_down;						//1-bit 0-Power Up 1-Power Down
	enum{
		VCO_POWER_UP = 0,
		VCO_POWER_DOWN
	}VCO_power_down_type;
	unsigned char mute_till_lock_detect;		//1-bit 0-Mute Disable 1-Mute Enable
	enum{
		MUTE_DISABLE = 0,
		MUTE_ENABLE
	}mute_till_lock_detect_type;
	unsigned char AUX_output_select;				//1-bit 0-Divided Output 1-Fundamental
	enum{
		DIVIDED_OUTPUTE = 0
		//FUNDAMENTAL
	}AUX_output_select_type;
	unsigned char AUX_output;								//1-bit 0-Disable 1-Enable
	unsigned char AUX_output_power;					//2-bit 0 to 3
	/*AUX OUTPUT POWER
	00 -4dBm
	01 -1dBm
	10 +2dBm
	11 +5dBm
	*/
	unsigned char RF_OUT;										//1-bit 0-Disable 1-Enable
	unsigned char output_power;							//2-bit
	/*OUTPUT POWER
	00 -4dBm
	01 -1dBm
	10 +2dBm
	11 +5dBm
	*/
	unsigned char LD_pin_mode;							//2-bit
	enum{
		LD_LOW = 0,
		DIGITAL_LOCK_DETECT,
		//LOW,
		LD_HIGH = 3
	}LD_pin_mode_type;
}PLL_CFG;
/* USER CODE END PV */
 
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
void Error_Handler(void);
static void MX_GPIO_Init(void);
static void MX_CRC_Init(void);
static void MX_IWDG_Init(void);
static void MX_TIM6_Init(void);
static void MX_TIM7_Init(void);
static void MX_WWDG_Init(void);
static void MX_SPI2_Init(void);
static void MX_NVIC_Init(void);
 
/* USER CODE BEGIN PFP */
/* Private function prototypes -----------------------------------------------*/
void PLL_Config(PLL_CFG *config);
void PLL_Init(void);
void PLL_Enable(void);
void PLL_Disable(void);
void PLL_RF_Enable(void);
void PLL_RF_Disable(void);
/* USER CODE END PFP */
 
/* USER CODE BEGIN 0 */
 
/* USER CODE END 0 */
 
int main(void)
{
 
  /* USER CODE BEGIN 1 */
	char a = 0;
  /* USER CODE END 1 */
 
  /* MCU Configuration----------------------------------------------------------*/
 
  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();
 
  /* Configure the system clock */
  SystemClock_Config();
 
  /* Initialize all configured peripherals */
  MX_GPIO_Init();
  MX_CRC_Init();
  MX_IWDG_Init();
  MX_TIM6_Init();
  MX_TIM7_Init();
  MX_WWDG_Init();
  MX_SPI2_Init();
 
  /* Initialize interrupts */
  MX_NVIC_Init();
 
  /* USER CODE BEGIN 2 */
	HAL_Delay(500);
	PLL_Init();
  /* USER CODE END 2 */
 
  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  while (1)
  {
  /* USER CODE END WHILE */
 
  /* USER CODE BEGIN 3 */
  }
  /* USER CODE END 3 */
 
}
 
/** System Clock Configuration
*/
void SystemClock_Config(void)
{
 
  RCC_OscInitTypeDef RCC_OscInitStruct;
  RCC_ClkInitTypeDef RCC_ClkInitStruct;
 
    /**Initializes the CPU, AHB and APB busses clocks 
    */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE;
  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
  RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
  RCC_OscInitStruct.LSIState = RCC_LSI_ON;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  {
    Error_Handler();
  }
 
    /**Initializes the CPU, AHB and APB busses clocks 
    */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
  {
    Error_Handler();
  }
 
    /**Configure the Systick interrupt time 
    */
  HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
 
    /**Configure the Systick 
    */
  HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
 
  /* SysTick_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
}
 
/** NVIC Configuration
*/
static void MX_NVIC_Init(void)
{
  /* EXTI9_5_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(EXTI9_5_IRQn, 0, 0);
  HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);
  /* EXTI15_10_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0);
  HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
  /* SPI2_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(SPI2_IRQn, 0, 0);
  HAL_NVIC_EnableIRQ(SPI2_IRQn);
}
 
/* CRC init function */
static void MX_CRC_Init(void)
{
 
  hcrc.Instance = CRC;
  if (HAL_CRC_Init(&hcrc) != HAL_OK)
  {
    Error_Handler();
  }
 
}
 
/* IWDG init function */
static void MX_IWDG_Init(void)
{
 
  hiwdg.Instance = IWDG;
  hiwdg.Init.Prescaler = IWDG_PRESCALER_4;
  hiwdg.Init.Reload = 4095;
  if (HAL_IWDG_Init(&hiwdg) != HAL_OK)
  {
    Error_Handler();
  }
 
}
 
/* SPI2 init function */
static void MX_SPI2_Init(void)
{
 
  hspi2.Instance = SPI2;
  hspi2.Init.Mode = SPI_MODE_MASTER;
  hspi2.Init.Direction = SPI_DIRECTION_2LINES;
  hspi2.Init.DataSize = SPI_DATASIZE_16BIT;
  hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
  hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
  hspi2.Init.NSS = SPI_NSS_SOFT;
  hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
  hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
  hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
  hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
  hspi2.Init.CRCPolynomial = 10;
  if (HAL_SPI_Init(&hspi2) != HAL_OK)
  {
    Error_Handler();
  }
 
}
 
/* TIM6 init function */
static void MX_TIM6_Init(void)
{
 
  TIM_MasterConfigTypeDef sMasterConfig;
 
  htim6.Instance = TIM6;
  htim6.Init.Prescaler = 0;
  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
  htim6.Init.Period = 0;
  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
  {
    Error_Handler();
  }
 
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
  {
    Error_Handler();
  }
 
}
 
/* TIM7 init function */
static void MX_TIM7_Init(void)
{
 
  TIM_MasterConfigTypeDef sMasterConfig;
 
  htim7.Instance = TIM7;
  htim7.Init.Prescaler = 0;
  htim7.Init.CounterMode = TIM_COUNTERMODE_UP;
  htim7.Init.Period = 0;
  if (HAL_TIM_Base_Init(&htim7) != HAL_OK)
  {
    Error_Handler();
  }
 
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
  if (HAL_TIMEx_MasterConfigSynchronization(&htim7, &sMasterConfig) != HAL_OK)
  {
    Error_Handler();
  }
 
}
 
/* WWDG init function */
static void MX_WWDG_Init(void)
{
 
  hwwdg.Instance = WWDG;
  hwwdg.Init.Prescaler = WWDG_PRESCALER_1;
  hwwdg.Init.Window = 64;
  hwwdg.Init.Counter = 64;
  if (HAL_WWDG_Init(&hwwdg) != HAL_OK)
  {
    Error_Handler();
  }
 
}
 
/** Configure pins as 
        * Analog 
        * Input 
        * Output
        * EVENT_OUT
        * EXTI
*/
static void MX_GPIO_Init(void)
{
 
  GPIO_InitTypeDef GPIO_InitStruct;
 
  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOC_CLK_ENABLE();
  __HAL_RCC_GPIOD_CLK_ENABLE();
  __HAL_RCC_GPIOA_CLK_ENABLE();
  __HAL_RCC_GPIOB_CLK_ENABLE();
 
  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOA, PLL_EN_Pin|RF_OUT_EN_Pin, GPIO_PIN_RESET);
 
  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(Load_Enable_GPIO_Port, Load_Enable_Pin, GPIO_PIN_SET);
 
  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(LED0_GPIO_Port, LED0_Pin, GPIO_PIN_SET);
 
  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET);
 
  /*Configure GPIO pins : PLL_EN_Pin RF_OUT_EN_Pin LED0_Pin */
  GPIO_InitStruct.Pin = PLL_EN_Pin|RF_OUT_EN_Pin|LED0_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
  /*Configure GPIO pin : Load_Enable_Pin */
  GPIO_InitStruct.Pin = Load_Enable_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
  HAL_GPIO_Init(Load_Enable_GPIO_Port, &GPIO_InitStruct);
 
  /*Configure GPIO pin : Digit_Lock_Detect_Pin */
  GPIO_InitStruct.Pin = Digit_Lock_Detect_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  HAL_GPIO_Init(Digit_Lock_Detect_GPIO_Port, &GPIO_InitStruct);
 
  /*Configure GPIO pin : Analog_Lock_Detect_Pin */
  GPIO_InitStruct.Pin = Analog_Lock_Detect_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  HAL_GPIO_Init(Analog_Lock_Detect_GPIO_Port, &GPIO_InitStruct);
 
  /*Configure GPIO pin : LED1_Pin */
  GPIO_InitStruct.Pin = LED1_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
  HAL_GPIO_Init(LED1_GPIO_Port, &GPIO_InitStruct);
 
}
 
/* USER CODE BEGIN 4 */
void PLL_Enable(void)
{
	HAL_GPIO_WritePin(PLL_EN_GPIO_Port,PLL_EN_Pin,GPIO_PIN_SET);
}
 
void PLL_Disable(void)
{
	HAL_GPIO_WritePin(PLL_EN_GPIO_Port,PLL_EN_Pin,GPIO_PIN_RESET);
}
 
void PLL_RF_Enable(void)
{
	HAL_GPIO_WritePin(RF_OUT_EN_GPIO_Port,RF_OUT_EN_Pin,GPIO_PIN_SET);
}
 
void PLL_RF_Disable(void)
{
	HAL_GPIO_WritePin(RF_OUT_EN_GPIO_Port,RF_OUT_EN_Pin,GPIO_PIN_RESET);
}
 
void PLL_Config(PLL_CFG *config)
{
	uint32_t Reg[6];
	uint8_t i;
	Reg[0] &= 0x00000000;
	Reg[0] |= ((uint32_t)config->integer_value 						< < 15)	& 0x7FFF8000;
	Reg[0] |= ((uint32_t)config->fractional_value 				< < 3)		& 0x00007FF8;
	Reg[0] |= 0x00000000;
	Reg[1] &= 0x00000000;
	Reg[1] |= ((uint32_t)config->phase_adjust 						< < 28)	& 0x10000000;
	Reg[1] |= ((uint32_t)config->prescaler 								< < 27)	& 0x08000000;
	Reg[1] |= ((uint32_t)config->phase_value 							< < 15)	& 0x07FF8000;
	Reg[1] |= ((uint32_t)config->modulus_value 						< < 3)		& 0x00007FF8;
	Reg[1] |= 0x00000001;
	Reg[2] &= 0x00000000;
	Reg[2] |= ((uint32_t)config->low_noise_and_low_spur 	< < 29)	& 0x60000000;
	Reg[2] |= ((uint32_t)config->muxout 									< < 26)	& 0x1C000000;
	Reg[2] |= ((uint32_t)config->reference_doubler 				< < 25)	& 0x02000000;
	Reg[2] |= ((uint32_t)config->reference_divide_by2 		< < 24)	& 0x01000000;
	Reg[2] |= ((uint32_t)config->r_counter 								< < 14)	& 0x00FFC000;
	Reg[2] |= ((uint32_t)config->double_buffer 						< < 13)	& 0x00002000;
	Reg[2] |= ((uint32_t)config->charge_pump_current 			< < 9)		& 0x00001E00;
	Reg[2] |= ((uint32_t)config->LDF 											< < 8)		& 0x00000100;
	Reg[2] |= ((uint32_t)config->LDP 											< < 7)		& 0x00000080;
	Reg[2] |= ((uint32_t)config->PD_polarity 							< < 6)		& 0x00000040;
	Reg[2] |= ((uint32_t)config->power_down 							< < 5)		& 0x00000020;
	Reg[2] |= ((uint32_t)config->CP_three_state 					< < 4)		& 0x00000010;
	Reg[2] |= ((uint32_t)config->counter_reset 						< < 3)		& 0x00000008;
	Reg[2] |= 0x00000002;
	Reg[3] &= 0x00000000;
	Reg[3] |= ((uint32_t)config->band_select_clock 				< < 23)	& 0x00800000;
	Reg[3] |= ((uint32_t)config->antibacklash_pulse_width < < 22)	& 0x00400000;
	Reg[3] |= ((uint32_t)config->charge_cancelation				< < 21)	& 0x00200000;
	Reg[3] |= ((uint32_t)config->cycle_slip_reduction			< < 18)	& 0x00040000;
	Reg[3] |= ((uint32_t)config->clk_div_mode							< < 15)	& 0x00018000;
	Reg[3] |= ((uint32_t)config->clock_divider_value			< < 3)		& 0x00007FF8;
	Reg[3] |= 0x00000003;
	Reg[4] &= 0x00000000;
	Reg[4] |= ((uint32_t)config->feedback_select					< < 23)	& 0x00800000;
	Reg[4] |= ((uint32_t)config->RF_divider_select				< < 20)	& 0x00700000;
	Reg[4] |= ((uint32_t)config->band_select_clock_divider< < 12)	& 0x000FF000;
	Reg[4] |= ((uint32_t)config->VCO_power_down						< < 11)	& 0x00000800;
	Reg[4] |= ((uint32_t)config->mute_till_lock_detect		< < 10)	& 0x00000400;
	Reg[4] |= ((uint32_t)config->AUX_output_select				< < 9)		& 0x00000200;
	Reg[4] |= ((uint32_t)config->AUX_output								< < 8)		& 0x00000100;
	Reg[4] |= ((uint32_t)config->AUX_output_power					< < 6)		& 0x000000C0;
	Reg[4] |= ((uint32_t)config->RF_OUT										< < 5)		& 0x00000020;
	Reg[4] |= ((uint32_t)config->output_power							< < 3)		& 0x00000018;
	Reg[4] |= 0x00000004;
	Reg[5] &= 0x00000000;
	Reg[5] |= ((uint32_t)config->LD_pin_mode							< < 22)	& 0x00C00000;
	Reg[5] |= 0x00180000;
	Reg[5] |= 0x00000005;
	for(i=0;i&lt;6;i++)
	{
		Reg[i] = ((Reg[i] >> 16) & 0x0000FFFF) | ((Reg[i] < < 16) & 0xFFFF0000); 
	}
	HAL_GPIO_WritePin(Load_Enable_GPIO_Port,Load_Enable_Pin,GPIO_PIN_RESET);
	HAL_SPI_Transmit(&PLL_PROT,(uint8_t*)&Reg[5],2,1000);
	HAL_GPIO_WritePin(Load_Enable_GPIO_Port,Load_Enable_Pin,GPIO_PIN_SET);
	HAL_GPIO_WritePin(Load_Enable_GPIO_Port,Load_Enable_Pin,GPIO_PIN_RESET);
	HAL_SPI_Transmit(&PLL_PROT,(uint8_t*)&Reg[4],2,1000);
	HAL_GPIO_WritePin(Load_Enable_GPIO_Port,Load_Enable_Pin,GPIO_PIN_SET);
	HAL_GPIO_WritePin(Load_Enable_GPIO_Port,Load_Enable_Pin,GPIO_PIN_RESET);
	HAL_SPI_Transmit(&PLL_PROT,(uint8_t*)&Reg[3],2,1000);
	HAL_GPIO_WritePin(Load_Enable_GPIO_Port,Load_Enable_Pin,GPIO_PIN_SET);
	HAL_GPIO_WritePin(Load_Enable_GPIO_Port,Load_Enable_Pin,GPIO_PIN_RESET);
	HAL_SPI_Transmit(&PLL_PROT,(uint8_t*)&Reg[2],2,1000);
	HAL_GPIO_WritePin(Load_Enable_GPIO_Port,Load_Enable_Pin,GPIO_PIN_SET);
	HAL_GPIO_WritePin(Load_Enable_GPIO_Port,Load_Enable_Pin,GPIO_PIN_RESET);
	HAL_SPI_Transmit(&PLL_PROT,(uint8_t*)&Reg[1],2,1000);
	HAL_GPIO_WritePin(Load_Enable_GPIO_Port,Load_Enable_Pin,GPIO_PIN_SET);
	HAL_GPIO_WritePin(Load_Enable_GPIO_Port,Load_Enable_Pin,GPIO_PIN_RESET);
	HAL_SPI_Transmit(&PLL_PROT,(uint8_t*)&Reg[0],2,1000);
	HAL_GPIO_WritePin(Load_Enable_GPIO_Port,Load_Enable_Pin,GPIO_PIN_SET);
}
 
void PLL_Init(void)
{
	PLL_CFG PLL_InitStruct;
	PLL_InitStruct.integer_value = 22000;
	PLL_InitStruct.fractional_value = 0;
	//
	PLL_InitStruct.phase_adjust = PHASE_ADJ_OFF;
	PLL_InitStruct.prescaler = PRESCALER_8Div9;
	PLL_InitStruct.phase_value = 0;
	PLL_InitStruct.modulus_value = 2;
	//
	PLL_InitStruct.low_noise_and_low_spur = LOW_NOISE;
	PLL_InitStruct.muxout = MUXOUT_ANALOG_LOCK_DETECT;
	PLL_InitStruct.reference_doubler = ENABLE;
	PLL_InitStruct.reference_divide_by2 = ENABLE;
	PLL_InitStruct.r_counter = 250;
	PLL_InitStruct.double_buffer = DISABLE;
	PLL_InitStruct.charge_pump_current = 7;
	PLL_InitStruct.LDF = INT_N;
	PLL_InitStruct.LDP = LDP_10ns;
	PLL_InitStruct.PD_polarity = POSITIVE;
	PLL_InitStruct.power_down = DISABLE;
	PLL_InitStruct.CP_three_state = DISABLE;
	PLL_InitStruct.counter_reset = DISABLE;
	//
	PLL_InitStruct.band_select_clock = LOW;
	PLL_InitStruct.antibacklash_pulse_width = INT_N;
	PLL_InitStruct.cycle_slip_reduction = DISABLE;
	PLL_InitStruct.clk_div_mode = FAST_LOCK_ENABLE;
	PLL_InitStruct.clock_divider_value = 4;
	//
	PLL_InitStruct.feedback_select = FUNDAMENTAL;
	PLL_InitStruct.RF_divider_select = 6;
	PLL_InitStruct.band_select_clock_divider = 80;
	PLL_InitStruct.VCO_power_down = VCO_POWER_UP;
	PLL_InitStruct.mute_till_lock_detect = MUTE_ENABLE;
	PLL_InitStruct.AUX_output_select = DIVIDED_OUTPUTE;
	PLL_InitStruct.AUX_output = DISABLE;
	PLL_InitStruct.AUX_output_power = 0;
	PLL_InitStruct.RF_OUT = ENABLE;
	PLL_InitStruct.output_power = 5;
	//
	PLL_InitStruct.LD_pin_mode = DIGITAL_LOCK_DETECT;
	//
	PLL_Enable();
	PLL_Config(&PLL_InitStruct);
}
 
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
	GPIO_PinState tmp;
	switch(GPIO_Pin)
	{
		case Digit_Lock_Detect_Pin:
			tmp = HAL_GPIO_ReadPin(Digit_Lock_Detect_GPIO_Port,Digit_Lock_Detect_Pin);
			HAL_GPIO_WritePin(LED0_GPIO_Port,LED0_Pin,!tmp);
			if(tmp == GPIO_PIN_SET)
			{
				PLL_RF_Enable();
			}
			break;
		case Analog_Lock_Detect_Pin:
			tmp = HAL_GPIO_ReadPin(Analog_Lock_Detect_GPIO_Port,Analog_Lock_Detect_Pin);
			HAL_GPIO_WritePin(LED1_GPIO_Port,LED1_Pin,!tmp);
			break;
	}
}
/* USER CODE END 4 */
 
/**
  * @brief  This function is executed in case of error occurrence.
  * @param  None
  * @retval None
  */
void Error_Handler(void)
{
  /* USER CODE BEGIN Error_Handler */
  /* User can add his own implementation to report the HAL error return state */
  while(1) 
  {
  }
  /* USER CODE END Error_Handler */ 
}
 
#ifdef USE_FULL_ASSERT
 
/**
   * @brief Reports the name of the source file and the source line number
   * where the assert_param error has occurred.
   * @param file: pointer to the source file name
   * @param line: assert_param error line source number
   * @retval None
   */
void assert_failed(uint8_t* file, uint32_t line)
{
  /* USER CODE BEGIN 6 */
  /* User can add his own implementation to report the file name and line number,
    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
  /* USER CODE END 6 */
 
}
 
#endif
 
/**
  * @}
  */ 
 
/**
  * @}
*/ 
 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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